A methodology for simulation of hybrid Single-electron/MOS transistor circuits

In the early days of microelectronic design, a top-to-down design fl ow was conceived to achieve the designs, while a bottom-up verifi cation path was used in order to check them during every stage of design with the aim of generating a series of EDA tools. In a near future, hybrid systems composed of nanometric CMOS transistors and nano-devices, such as the SET will also need the development of a counterpart of their own design and verifi cation paths. It is regarding the last one, that a simulation methodology is devised in order to determine their electric response. The main current obstacle when establishing a simulation strategy of hybrid systems consists in dealing with the big gap in development of both worlds, that is to say, the simulation methodology for CMOS circuits is mature even considering the new issues regarding the nanometric dimensions of the devices; while the simulation methodology for SET structures is still in its infancy. A simulation methodology for hybrid systems must cope with this circumstance while providing a reliable verifi cation of the electric behaviour of the MOS/SET circuitry in a scheme that should be appealing for nowadays circuit designers. By considering this aspect, a particularly straightforward verifi cation strategy for hybrid systems composed of SET devices and CMOS consists in establishing models for the SET that can be easily combined with the MOS models that are embedded in SPICE-like simulators.